1. Field of the Invention
The present invention relates to semiconductor memory arrays, and particularly to three-dimensional passive element memory arrays.
2. Description of the Related Art
Integrated circuits incorporating a passive element memory array require a high-voltage and high-current programming voltage source due to the large number of leakage paths in the array and the high voltage required to program the element conductivity. The leakage current represents a significant portion of the power dissipation of such circuits during programming. There remains a need for improved performance of such circuits, reduced leakage currents when writing, and faster write time of a selected memory cell.
An improved passive element memory array biases unselected X-lines to one voltage, and biases unselected Y-lines to another voltage, both having a value less than the programming voltage. In a preferred embodiment, four voltage levels are applied to the array to bias the array for write mode: 1) a programming (VPP) voltage applied to the selected X-line; 2) a somewhat lower voltage equal to VPP minus a first offset voltage applied to the unselected Y-lines; 3) a voltage equal to a second offset voltage (relative to ground) applied to the unselected X-lines; and 4) a ground reference voltage applied to the selected Y-line. The first and second offset voltages preferably are identical and have a value of about 0.5 to 2 volts. The VPP voltage depends upon the memory cell technology used, and preferably falls within the range of 5 to 20 volts.
The respective bias voltages are preferably applied to the unselected X-lines and the unselected Y-lines before the selected X-line and selected Y-line are driven to place the programming voltage VPP across the selected memory cell. As a result, the unselected X-lines and Y-lines in the array are already biased before the selected X-line is driven, and the rise time of the selected X-line (e.g., during its transition from ground or the offset voltage above ground to VPP) may be accomplished much faster. Leakage currents through the unselected memory cells in the array are now provided by the bias voltage sources, and are no longer provided by current flow through the selected X-line and Y-line. Consequently, the magnitude of the current traversing through the selected X-line and Y-line is much lower and results in less voltage drop due to the distributed resistance of the selected X-line and Y-line. For a required programming voltage impressed across a selected memory cell, the VPP voltage need not be quite as large since a greater portion of the VPP voltage actually reaches the selected memory cell.
The high voltage source required to program the memory cells may be generated on-chip by a VPP generator, sometimes frequently implemented as charge pump circuits. However, the chip area required by such on-chip circuitry to generate the programming voltage source with enough current capability to support the leakage current of unselected memory cells is substantial. Alternatively, an external source of the VPP programming voltage is provided, which reduces the area otherwise required for an on-chip VPP generator and saves the power that would be consumed by such a generator. In addition, the operating temperature of the integrated circuit during the programming operation decreases, and reduces the leakage current through the reverse biased unselected memory cells. As a result, the total power consumption is reduced by quite a bit more than just the savings achieved by removing the VPP generator circuit.
By removing the VPP generator, a higher value for VPP may be used with the same semiconductor process, which allows much faster programming. Alternatively, for a given voltage necessary to program a particular memory cell technology, the overall voltage requirements of the semiconductor technology may be relaxed. This may allow an even greater savings in integrated circuit area, as the spacing between various on-chip structures may be reduced. Preferably, the programming voltage received from an external voltage source is the highest voltage conveyed anywhere in the chip, and other bias voltages may either be received from other external voltage sources or generated using on-chip circuitry.
When discharging the memory array, the capacitance between layers (i.e., between memory array lines on adjacent layers), in particular the substantial capacitance from the unselected Y-lines to adjacent unselected X-lines, is preferably discharged first by driving their X-lines and Y-lines to nearly the same voltage. The array lines may then be safely discharged to ground without coupling array lines on adjacent layers below ground and potentially causing a CMOS latchup event to occur.
The invention is particularly applicable to a passive element array having an antifuse and diode in series as the memory element, but is also applicable to other passive element memory arrays. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.